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1 |  |  | JM20330 Datasheet Rev 3.0 | JMH330 Datasheet Rev 3.5 | Rohm BU29504KV Datasheet Rev 0.97 | SunPlus SPIF223A Datasheet
2 | Pin # |  | Name | Type | Description | Name | Type | Description | Name | Type | Description | Name | Type | Description
3 | 22 |  | XTALI | AI | Crystal Input/Oscillator Input. It is connected to a 25MHz crystal or crystal oscillator, frequency tolerance ±50ppm. | XTALI | AI | Crystal Input/Oscillator Input. It is connected to a 25MHz crystal or crystal oscillator, frequency tolerance ±50ppm. | XTALI | AI | Crystal Oscillation Circuit Input: 25MHz crystal oscillator shall be connected externally. | XTALI/CLKI | I | Crystal oscillator input or external clock input
4 | 23 |  | XTALO | AO | Crystal Output. It is connected to a crystal. While crystal oscillator is applied, this pin should be reserved as No Connection (NC). | XTALO | AO | Crystal Output. It is connected to a crystal. While crystal oscillator is applied, this pin should be reserved as No Connection (NC). | XTALO | AO | Crystal Oscillation Circuit Output | XTALO | O | Crystal oscillator output
5 | 26 |  | REXT | AI | External Reference Resistance. An external 12KΩ1% (12.1 KΩ 1%) resistor should be connected and bypass to the analog ground. (Note 1) | REXT | AI | External Reference Resistance. An external 12KΩ1% (12.1 KΩ 1%) resistor should be connected and bypass to the analog ground. (Note 1) | REXT | AI | External Reference Resistor Connection Input: As the reference, a resistor with 11.3/10KΩ should be connected to ground. The accuracy of resistor must be within ±1% (ref. Figure 8-1). | REXT | I | External reference resistor input
6 | 27 |  | RXP | AI | Serial Data Receiver. It receives positive input of differential signal. | RXP | AI | Serial Data Receiver. It receives positive input of differential signal. | RXP | AI | Serial Data Receiver: Differential input signal: 1.5Gbps Only AC connection shall be supported. | RXP | I | Differential receive +ve
7 | 28 |  | RXN | AI | Serial Data Receiver. It receives negative input of differential signal. | RXN | AI | Serial Data Receiver. It receives negative input of differential signal. | RXN | AI | Serial Data Receiver: Differential input signal: 1.5Gbps Only AC connection shall be supported. | RXN | I | Differential receive –ve
8 | 32 |  | TXP | AO | Serial Data Transmitter. It transmits positive output of differential signal. | TXP | AO | Serial Data Transmitter. It transmits positive output of differential signal. | TXP | AO | Serial Data Transmitter: Differential output signal: 1.5Gbps Only AC connection shall be supported. | TXP | O | Differential transmit +ve
9 | 31 |  | TXN | AO | Serial Data Transmitter. It transmits negative output of differential signal. | TXN | AO | Serial Data Transmitter. It transmits negative output of differential signal. | TXN | AO | Serial Data Transmitter: Differential output signal: 1.5Gbps Only AC connection shall be supported. | TXN | O | Differential transmit –ve
10 | 61, 63, 1, 3, 6, 10, 12, 14, 15, 13, 11, 7, 5, 2, 64, 62 |  | DD[15:0] | DIO | Data Bus. This is a bi-directional data bus for a host and a device to transfer data, command, and status. | DD[15:0] | DIO | Data Bus. This is a bi-directional data bus for a host and a device to transfer data, command, and status. | DD[15:0] | Pins 3 and 11 are DIOL All others are DIO | ATA/ATAPI Data Bus: ATA/ATAPI Bi-directional Data Bus. | B_IDE_DD[15:0] | IO | ATA Interface Data Bus
11 | 47,48 |  | CSn[1:0] | DIO | Chip Select. Active-low signals from a host to select a Command Block or Control Block register of a device. | CSn[1:0] | DIO | Chip Select. Active-low signals from a host to select a Command Block or Control Block register of a device. | CSn[1:0] | DIO | ATA/ATAPI Chip Select: [Host mode: In, Device mode: Out] Chip select signal for the device register access. | IDE_CS[1:0]_B | IO | ATA Interface Chip Select
12 | 49, 51, 50 |  | DA[2:0] | DIO | Device Address. Address signals from a host to access a register or data port of the device. | DA[2:0] | DIO | Device Address. Address signals from a host to access a register or data port of the device. | DA[2:0] | DIO | ATA/ATAPI Data Address: [Host mode: In, Device mode: Out] Address signal for data access. | IDE_DA[2:0] | IO | ATA Interface Device Address
13 | 58 |  | DIORn/ HDMARDYn/ HSTROBE | DIO | IO Read/Ultra DMA Ready/Ultra DMA Data Strobe. DIORn: Active-low signal from a host to read a register or data port of a device. HDMARDYn: Active-low signal from a host to indicate its ready to receive Ultra DMA data-in burst from a device. HSTROBE: Signal from a host to latch data into a device at Ultra DMA data-out operation. | DIORn/ HDMARDYn/ HSTROBE | DIO | IO Read/Ultra DMA Ready/Ultra DMA Data Strobe. DIORn: Active-low signal from a host to read a register or data port of a device. HDMARDYn: Active-low signal from a host to indicate its ready to receive Ultra DMA data-in burst from a device. HSTROBE: Signal from a host to latch data into a device at Ultra DMA data-out operation. | DIORn/ HDMARDYn/ HSTROBE | DIO | IO Read / UDMA Ready / UDMA Data Strobe: [Host mode: In, Device mode: Out] - At UDMA transfer: Functions as HDMARDYn (at reading) / HSTROBE (at writing) signal. Notification signal for ‘Ready to Receive Data’ when reading. Strobe signal for data latch timing when writing. - Other than UDMA transfer: Functions as DIORn. (Register data reading signal) | IDE_DIOR_B | IO | ATA Interface I/O Read ATA Interface DMA Ready during Ultra DMA data-in bursts ATA Interface Data Strobe during Ultra DMA data-out bursts
14 | 59 |  | DIOWn/ STOP | DIO | IO Write/Stop Ultra DMA Burst. DIOWn: Active-low signal from a host to write a register or data port of a device. STOP: Active-high signal from a host to terminate an Ultra DMA transfer. | DIOWn/ STOP | DIO | IO Write/Stop Ultra DMA Burst. DIOWn: Active-low signal from a host to write a register or data port of a device. STOP: Active-high signal from a host to terminate an Ultra DMA transfer. | DIOWn/ STOP | DIO | IO Write / UDMA Stop: [Host mode: In, Device mode: Out] - At UDMA transfer: Functions as a STOP signal. (Data transfer stop requesting signal) - Other than UDMA transfer: Functions as DIOWn. (Register data writing signal) | IDE_DIOW_B | IO | ATA Interface I/O Write ATA Interface Stop during Ultra DMA data bursts
15 | 54 |  | DMACKn | DIO | DMA Acknowledge. Active-low signal from a host to acknowledge the DMA request from a device. | DMACKn | DIO | DMA Acknowledge. Active-low signal from a host to acknowledge the DMA request from a device. | DMACKn | DIO | DMA Acknowledge: [Host mode: In, Device mode: Out] Used at DMA transfer. Answering signal for data transfer start which the Host responds to the DMARQ signal (60 pin) from the device side. | IDE_DMACK_B | IO | ATA Interface DMA Acknowledge
16 | 60 |  | DMARQ | DIO | DMA Request. Active-high signal from a device to request a DMA transfer. | DMARQ | DIO | DMA Request. Active-high signal from a device to request a DMA transfer. | DMARQ | DIOL | DMA Request: [Host mode: Out, Device mode: In] Used at DMA transfer. Data transfer start requesting signal from the Device side to Host side. | IDE_DMARQ | IO | ATA Interface DMA Request
17 | 53 |  | INTRQ | DIO | Device Interrupt. Active-high signal from a device to interrupt a host. | INTRQ | DIO | Device Interrupt. Active-high signal from a device to interrupt a host. | INTRQ | DIO | Device Interrupt: [Host mode: Out, Device mode: In] Interruption requesting signal from the device side. | IDE_INTRQ | IO | ATA Interface Interrupt Request
18 | 55 |  | IORDY/ DDMARDYn/ DSTROBE | DIO | IO Ready/Ultra DMA Ready/Ultra DMA Data Strobe. IORDY: Active-high signal from a device to extend the host cycle time for operation at PIO mode 3 and above. DDMARDYn: Active-low signal from a device used to indicate its ready to receive Ultra DMA data-out burst from a host. DSTROBE: Signal from a device used to latch data into a host at Ultra DMA data-in operation. | IORDY/ DDMARDYn/ DSTROBE | DIO | IO Ready/Ultra DMA Ready/Ultra DMA Data Strobe. IORDY: Active-high signal from a device to extend the host cycle time for operation at PIO mode 3 and above. DDMARDYn: Active-low signal from a device used to indicate its ready to receive Ultra DMA data-out burst from a host. DSTROBE: Signal from a device used to latch data into a host at Ultra DMA data-in operation. | IORDY/ DDMARDYn/ DSTROBE | DIO | IORDY / DDMARDY / DSTROBE: [Host mode: Out, Device mode: In] - At UDMA transfer: Functions as DDMARDYn (at writing)/DSTROBE (at reading) signal. Notification signal for ‘Ready to Receive Data’ when writing. Strobe signal for data latch timing when reading. - Other then UDMA transfer: Functions as IORDY signal. Wait requesting signal from the Device side. | IDE_IORDY | IO | ATA Interface I/O Ready ATA Interface DMA Read during Ultra DMA data-out bursts ATA Interface Data Strobe during Ultra DMA data-in bursts
19 | 46 |  | PDIAGn/ PATAOR | DIOH | Diagnostic Signal. In Host Bridge mode: PDIAGn provides the diagnostic signals from device 1 to device 0 to indicate the device 1 diagnosis is complete. In Device mode: PATAOR defines the pin order of parallel ATA interface. (see 5.6) 0: ATA interface signals in Normal Order mode. 1: ATA interface signals in Reverse Order mode. | PDIAGn/ PATAOR | DIOH | Diagnostic Signal. PDIAGn provides the diagnostic signals from device 1 to device 0 to indicate the device 1 diagnosis is complete. | PDIAGn | DIOH | Pass Diagnostics / Parallel ATA Bus Order Reverse: - In the Host mode: Functions as PDIAGn signal. Notification signal for the results of the self-diagnostic from Slave to Master. - In the Device mode [Only valid for BU29504]: Bus switching signal for the Parallel ATA (ref. Table 5-1). 0: ATA interface (in the Normal Order mode) 1: ATA interface (in the Reverse Order mode) CBLID - No functionality | IDE_PDIAG | IO | ATA Interface Passed Diagnostics ATA Interface Cable Assembly Type Identifier
20 | 16 |  | RESETn | DIO | Hardware Reset. Active-low signal from a host to reset a device. | RESETn | DIO | Hardware Reset. Active-low signal from a host to reset a device. | RESETn | DIO | Hardware Reset: [Host mode: In, Device mode: Out] Resetting signal from the Host to Device side (Active Low). | I_IDE_RST_B | IO | ATA Interface Reset.
21 | 34 |  | DASPn | DIOH | Slave Device Present. Active-low signal from Device 1 to Device 0 in Host Bridge mode to indicate the presence of slave device. In Device 0: configuration, this pin is an input. In Device 1: configuration, it is an output. This pin is used as slave present indicator at ATA power on device diagnostics phase, and used as device activity at command or data transfer. In Device Bridge mode, the pin is output (reserved). | DASPn | DIOH | Slave Device Present. Active-low signal from Device 1 to Device 0 that indicate the presence of slave device. In Device 0 configuration, this pin is an input. | DASPn | DIOH | Slave Present / Device Active [In the Host mode only] - At operating a reset protocol: Functions as DASPn signal. (Present signal from the Slave to Master) [Active Low / Master: In, Slave: Out] (Also refer to the MSSEL Signal Pin.) - After operating the reset protocol: Signal for Device Active indicator. | IDE_DASP | IO | ATA Interface Device Active or Slave(Device 1) Present
22 | 52 |  | SP | DIOL | Slave Device Present. Active-high signal from Device 1 to Device 0 in Host Bridge mode to indicate the presence of slave device. In Device 0 configuration, this pin is an input. In Device 1 configuration, it is an output. In Device Bridge mode, SP is cable detection pin, default setting is used 80-conductor cable. 0: 80-conductor cable is detected. 1: 40-conductor cable is detected. | SP | DIL | Special internal test Pin. No connect. | SP | DIOL | Slave Present [In the Host mode only] Present signal from the Slave to Master. Same functions as DASPn (34 pin). However, it operates as a present signal, except for the Reset protocol.. Mainly used when hot swapping is functioning. [Active Hi (PHYRDY output) / Master: In, Slave: Out] (Also refer to the MSSEL Signal Pin.) | IDE_CSEL | IO | ATA Interface Cable Select
23 | 24 |  | AVDDH | AI | Analog Power. Analog 3.3V power supply. It should be bypassed to ground by a 0.1uF capacitance. | AVDDH | AI | Analog Power. Analog 3.3V power supply. It should be bypassed to ground by a 0.1uF capacitance. | AVDDH | AI | 3.3V Analog Power Supply | VDDA | PWR | 1.8V Analog Power
24 | 29 |  | AVDDL | AI | Analog Power. Analog 1.8V power supply. It should be bypassed to ground by a 0.1uF capacitance. | AVDDL | AI | Analog Power. Analog 1.8V power supply. It should be bypassed to ground by a 0.1uF capacitance. | AVDDL | AI | 1.8V / 1.2V (ref. Table 2-1) Analog power supply | VDDA | PWR | 1.8V Analog Power
25 | 25, 30 |  | AGND | AI | Analog Ground | AGND | AI | Analog Ground | AGND | AI | Analog GND | GNDA | GND | Analog Ground
26 | 4, 44 |  | VCCO | DI | Digital IO Power. Digital 3.3V power supply. It should be bypassed to ground by a 0.1uF capacitance. | VCCO | DI | Digital IO Power. Digital 3.3V power supply. It should be bypassed to ground by a 0.1uF capacitance. | VCCO | DI | 3.3V I/O Power Supply | D3V3_IO | PWR | 3.3V Digital I/O Power
27 | 9 |  | VCCK | DI | Digital Core Power. Digital 1.8V power supply. It should be bypassed to ground by a 0.1uF capacitance. | VCCK | DI | Digital Core Power. Digital 1.8V power supply. It should be bypassed to ground by a 0.1uF capacitance. | VCCK | DI | 1.8V / 1.2V (ref. Table 2-1) Core power supply | D1V8_CO | PWR | 1.8V Digital CORE Power
28 | 41 |
29 | 56 |  | D3V3_IO | PWR | 3.3V Digital I/O Power
30 | 8, 42, 57 |  | DGND | DI | Digital ground. | DGND | DI | Digital ground. | DGND | DI | Digital GND | DVSS | GND | Ground for the Digital Core and I/O
31 | 17 |  | PORn | DIH | Power On Reset. Low-active global reset. It should be connected to an external RC to build the power on initialization. | PORn | DIH | Power On Reset. Low-active global reset. It should be connected to an external RC to build the power on initialization. | PORn | DIH | Power On Reset: Chip resetting signal (Active Low). | RESET_B | I | ASIC Reset input
32 | 35 |  | SSCEN | DIL | Spread Spectrum Clock Enable. 0: Disable SATA spread spectrum clocking. (default) 1: Enable SATA spread spectrum clocking. | RSVDL | DIL | Reserved pin, it must be set to low. | SSCEN | DIL | Spread Spectrum Clock Enable: Control signal for spread spectrum clock function. 0: Invalidate the spread spectrum clock function (default). 1: validate the spread spectrum clock function. | IDE_JUMP1 | I | Jumper 1
33 | 37 |  | CLKSEL[1:0] | DIL | Reference Clock Selection. 01: 25MHz external reference clock. others: reserved. | CLKSEL[1:0] | DIL | Reference Clock Selection. 01: 25MHz external reference clock. others: reserved. | CLKSEL[1:0] | DIL | Reference Clock Selection: Frequency setting for crystal oscillator. 01: 25MHz external crystal oscillator (default). Others: Reserved. | UAO_SPI_OUT | O | UART/SPI data output
34 | 36 |  | DIH | DIH | DIH | TEST_CFG | I | Test Configuration bit 0
35 | 40 |  | PHYRDY | DO | Physical Layer Ready. 0: Serial ATA physical layer communication is not established. 1: Serial ATA physical layer communication is established. | PHYRDY | DO | Physical Layer Ready. 0: Serial ATA physical layer communication is not established. 1: Serial ATA physical layer communication is established. | PHYRDY | DOL | Physical Layer Ready: Communication establishment signal after completion of an initialization for the Serial ATA PHY layer. 0: Right after POR or when initialization failed for the Physical layer. 1: Initialization for the PHY layer has completed. | UAI_SPI_IN | I | UART/SPI data in
36 | 20 |  | MODE[2:0] | DIL | Mode [2]: select Host/Device bridge mode. 0: Device bridge mode. 1: Host bridge mode. Mode [1:0]: select UDMA speed when FXDMA is set. 00: 100MB/s. 01: 133MB/s. 10: 150MB/s. (default) 11: Reserved. MODE[1:0] must never be set to “11” and shall never be left floating!! External Pull resistor must be added!! | RSVDH | DIL | Reserved pin, it must be set to high. | MODE[2] | DIL | Mode Selection: Selection of the Host mode / Device mode. 0: Device mode (default) 1: Host mode | CFG0 | I | Device/Host mode enable
37 | 19 |  | DIH | MODE[1:0] | DIL | Ultra DMA operation rate. Mode [1:0]: select UDMA speed when FXDMA is set. 00: 100MB/s. 01: 133MB/s. 10: 150MB/s. (default) 11: Reserved. MODE[1:0] must never be set to “11” and shall never be left floating!! External Pull resistor must be added!! | MODE[1:0] | DIH | Mode Selection: (for TEST) For fixing a data transfer rate, also need to set FXDMA (38 pin). 00: 100MB/s 01: 133MB/s 10: 150MB/s (default) 11: Reserved (LSI test mode) | IDE_ORD_INV | I | ATA Cable Signal Ordering Inverse
38 | 18 |  | DIL | DIH | DIL | D3V3_IO | PWR | 3.3V Digital I/O Power
39 | 33 |  | MSSEL | DIOL | Master/Slave Selection. In Host Bridge mode: 0: Device 0 configuration. (default) 1: Device 1 configuration. In Device Bridge mode, the pin is output (reserved). | RSVDL | DIL | Reserved pin, it must be set to low. | MSSEL | DIOL | Master Slave Selection: [Host mode: In, Device mode: Out] - In the Host mode: 0: Master (default) 1: Slave (reserved) - In the Device mode: Data bit 4 of the Parallel ATA control register is output. | I_IDE_JUMP0 | I | Jumper 0
40 | 38 |  | FXDMA | DIL | Fixed UDMA Data Rate. 0: Adjustable Ultra DMA data rate according to SET FEATURE command (EFh). 1: Negate SET FEATURE command, and fix Ultra DMA data rate specified by MODE[1:0] setting. | FXDMA | DIL | Fixed UDMA Data Rate. 0: Adjustable Ultra DMA data rate according to SET FEATURE command (EFh). 1: Negate SET FEATURE command, and fix Ultra DMA data rate specified by MODE[1:0] setting. | FXDMA | DIL | Fixed UDMA Data Rate: (for TEST) Forced setting of the transfer rate. 0: Settable by Set Feature command (default). 1: Fixed setting of the data transfer rate by MODE [1:0] (18,19 pin). | SPI_En_B | O | SPI Enable
41 | 21 |  | ATAIOEN | DIH | ATA IO Interface Enable. 0: Disable the ATA output pins, present ATA I/O output pins are Hi-Z. 1: Enable the ATA output pins. | ATAIOEN | DIH | ATA IO Interface Enable. 0: Disable the ATA output pins, present ATA I/O output pins are Hi-Z. 1: Enable the ATA output pins. | ATAIOEN | DIH | ATA IO Interface Enable: Forced setting of the Hi impedance output for ATA IO Pin. 0: Valid (Hi impedance mode) 1: Invalid (default) | UART_SPI_SEL | I | UART/SPI interface enable 0: UART enable, 1: SPI enable
42 | 39 |  | PMEN | DIH | Power Management Command Enable. (reference 7.0) 0: Disable translating ATA Power Management feature command to Serial ATA Slumber mode. 1: Enable translating ATA Power Management feature command to Serial ATA Slumber mode. | PMEN | DIH | Power Management Command Enable. (reference 7.0) 0: Disable translating ATA Power Management feature command to Serial ATA Slumber mode. 1: Enable translating ATA Power Management feature command to Serial ATA Slumber mode. | PMEN | DIH | Power Management Command Enable: Power saving mode setting for the Serial ATA by ATA Power Management Feature Setting command. 0: Invalid 1: Valid (default) | SPL_CLK | O | SPI Clock
43 | 43 |  | UAI | DIH | On-chip UART input used for internal debugging. | UAI | DIH | On-chip UART input used for internal debugging. | UAI | DIH | On-Chip UART Input | I2C_SDA | IO | I2C Serial Data
44 | 45 |  | UAO | DOH | On-chip UART output used for internal debugging. | UAO | DOH | On-chip UART output used for internal debugging. | UAO | DOH | On-Chip UART Output | I2C_SCLK | IO | I2C Serial Clock